New

ASIC Engineering Technical Leader

Cisco Systems, Inc.
United States, California, San Jose
170 W Tasman Dr (Show on map)
Oct 17, 2025
The application window is expected to close on: October 21, 2025 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This role requires being onsite in San Jose, CA 4+ days/week. Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and cafe, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will also have an opportunity to work with other ASIC teams in the journey of taking it from concept to first customer shipments. Your Impact As a Design/CDC Engineer, you will specialize in clock domain crossing (CDC) analysis and closure, while also contributing to RTL design and microarchitecture development. You will ensure robust and reliable timing across multiple clock domains in complex chip designs, set up and optimize CDC analysis tools and methodologies, and collaborate closely with RTL designers and physical design teams. Responsibilities include: Participate in and contribute to chip architecture definition and discussions. Author design specifications and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing and performance requirements. Collaborate with the verification team to address design bugs and close code coverage. Lead CDC analysis efforts by setting up and maintaining CDC verification and closure tools to identify and resolve clock domain crossing issues early in the design cycle. Review and validate CDC-related synchronization schemes, clock domain definitions, and SDC constraints, and drive full-chip CDC closure efforts. Mentor RTL design owners on CDC analysis techniques, microarchitecture implications, and tool usage to improve design robustness. Minimum Qualifications: Bachelor's Degree in Electrical or Computer Engineering with 12+ years of ASIC or related experience or Master's Degree in Electrical or Computer Engineering with 8+ years of ASIC or related experience. Experience with microarchitecture and RTL implementation. Experience with digital design concepts (eg. clocking and async boundaries). Experience with synthesis tools (eg. Synopsys DC/DCG/FC) and Verilog/System Verilog programming. Preferred Qualifications: Experience in SDC constraint development. Experience with Spyglass CDC and glitch analysis. Experience with STA tools such as PrimeTime/Tempus. Experience with scripting languages such as Python, Perl, or TCL. Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.